This invention relates to coherent data demodulators for the demodulation of shift keyed signals which are phase-modulated to represent multibit data symbols.
The invention relates more particularly to such coherent data demodulators of a type in which, in the demodulation process, two quadrature phased channel signals are produced by separately multiplying together an incoming shift keyed signal of a given carrier frequency and each of two quadrature phased versions of a locally generated carrier signal of nominally the same frequency as said carrier frequency.
In a demodulator of the above type data symbols can thereafter be detected from either the incoming shift keyed signal or from either one of the two channel signals by determining the occurrence of transitions therein relative to those in a locally generated baud rate clock signal.
In order to achieve reliable data detection, both the locally generated carrier signal and the locally generated baud rate signal clock are required to be continuously adjusted into coherent phase relationship with the incoming shift keyed signal. This adjustment can be accomplished by using digital phase-locked loops (DPLL). A single DPLL can be used for both those adjustments, or they can be carried out using separate DPLL's in a carrier timing recovery circuit and a baud rate timing recovery circuit, respectively.
The article "A survey of Digital Phase-Locked Loops", published in Proceedings of the IEEE, Vol. 69, No. 4, April 1981, gives useful information on the state of the art.
Because the digital data is in the form of differently phased multi-bit (e.g., dibit) symbols, it becomes necessary to detect when a change in phase between adjacent symbols has occurred in order to recover the data. The detection requires an accurate relationship between the symbol or baud rate timing of the incoming signal and that of the locally generated baud rate clock. Phase information related to the baud rate timing is present as the position of all the transitions in the incoming signal and can be used to derive an estimate of the baud rate timing by averaging the occurrence of all these transitions over a relatively long period.
In a data demodulator of the above type these transitions which can be used for baud rate timing recovery are also present in each of the two channel signals and also in the resultant baseband signal as constituted by binary data in the detected symbols.
Using the incoming shift keyed signal for the recovery of the baud rate timing has the advantage that since this signal has not yet been processed at all, it contains all the information about the phase transitions. However, using the incoming shift keyed signal has the disadvantages that the carrier information is still present and must be removed and that because the signal has not been processed (except possibly by a receive filter) the signal is likely to be corrupted by noise.
The requirement of removing high frequency noise from the incoming shift keyed signal implies a need for a high sampling rate, while the requirement of averaging transitions over a long period implies a need for a low sampling rate. This necessitates either using a data demodulator with a high sampling rate front end, followed by a low sampling rate PLL, or using a high sampling rate throughout the demodulator, with a consequential increase in the complexity and hence the cost of the demodulator. Since the carrier information has to be removed to recover the baseband signal, it is thought more appropriate to derive the input to the baud rate timing recovery circuit at some point after the recovery of the carrier information, in order to take advantage of filtering introduced by the carrier timing recovery circuit. However, using one of the two channel signals still has the disadvantage that although the carrier information has been removed therefrom a twice carrier frequency component is present therein as a result of the multiplying process and, also, the noise introduced by transmission is still present.
Recovery of the baud rate timing using the resultant baseband signal overcomes the abovementioned disadvantages of noise and high-frequency sampling, but the use of this signal gives rise to difficulties in that the sample rate is low (e.g. in a proposed data system it is only twice the carrier frequency which amounts to only four samples per baud period), and in that the PLL for the carrier timing recovery circuit can lock up at different points in such a way (as will be described) as to alter the instant in time at which the data transitions occur relative to the actual baud rate transitions, thereby causing different sampling points to be seen by the baud rate timing recovery circuit.
The first of these two difficulties can be overcome to a material extent by using a long time constant for the PLL in the baud rate timing recovery circuit: this helps to remove the affect of the low sampling rate at the input to the circuits by effectively averaging out over time the quantisation error in the positions of the transitions.